1. Field of the Invention
The present invention relates to a pattern data creating method, a pattern data creating program, and a semiconductor device manufacturing method.
2. Description of the Related Art
According to the refining of semiconductor integrated circuits in recent years, a dimension equal to or larger than a half of a light source wavelength of a light exposing device is demanded as a minimum line width on the semiconductor integrated circuits. Because of such refining, a phenomenon in which, even if a mask pattern formed on a photomask as specified by a circuit design drawing is exposed to light and transferred onto a wafer, a pattern of a desired shape cannot be transferred, i.e., a phenomenon called optical proximity effect is becoming obvious. To solve such a problem, a technique for finishing a shape after transfer as specified by a desired design pattern when a mask pattern formed on a photomask is transferred onto a wafer (hereinafter, “optical proximity correction (OPC)”) is generally carried out. When the OPC is used, lithography verification for evaluating whether a circuit pattern exactly the same as a design pattern can be formed by a mask pattern manufactured through the OPC is performed (see, for example, Japanese Patent Application Laid-Open No. 2007-57948).
In semiconductor manufacturing processes such as lithography and etching processes, other circuit patterns arranged around a circuit pattern desired to be formed (hereinafter, “peripheral patterns”) substantially affect dimension accuracy of the circuit pattern desired to be formed. Therefore, process evaluation is performed with conceivable finite number of peripheral patterns arranged around the circuit pattern desired to be formed and correction or the like of the circuit pattern desired to be formed is performed to prevent problems from occurring.
However, even if no problem occurs in the process evaluation by the arrangement of the finite number of peripheral patterns in the past, an unexpected fatal error may occur in process evaluation in designing because of an unassumed arrangement variation (a peripheral pattern environment) in an actual product. To prevent such an error, it is acceptable if evaluation by a peripheral pattern environment assumed for an evaluation target cell pattern ends in a realistic evaluation time. However, when variations of cells and patterns arranged around the circuit pattern desired to be formed are infinitely assumed, it is impossible to realistically evaluate the variations.